RISC-V Boot Process: One Step at a Time - Atish Kumar Patra, Western Digital
A well-supported and standard boot flow is very important for the RISC-V software ecosystem before RISC-V can be a truly competitive alternative to existing mainstream ISAs. However, RISC-V also needs …
| Talk Title | RISC-V Boot Process: One Step at a Time - Atish Kumar Patra, Western Digital |
| Speakers | ATISH KUMAR PATRA (Principal R&D Engineer, Western Digital) |
| Conference | Open Source Summit + ELC Europe |
| Conf Tag | |
| Location | Lyon, France |
| Date | Oct 27-Nov 1, 2019 |
| URL | Talk Page |
| Slides | Talk Slides |
| Video | |
A well-supported and standard boot flow is very important for the RISC-V software ecosystem before RISC-V can be a truly competitive alternative to existing mainstream ISAs. However, RISC-V also needs its own trusted firmware to handle RISC-V specific features such as Supervisor Binary Interface (SBI) that allows the operating systems to interact with the supervisor execution environment (SEE). In this talk, Atish will discuss the status of a separate but modular open source SBI implementation (aka OpenSBI) that provides RISC-V specific run time services and how it helps in porting other common boot loaders such as U-Boot, coreboot and EDK2 to RISC-V. He will also discuss how the RISC-V boot process compares to other ISAs and where the community is heading.
